1. Field of the Invention
This invention relates to a semiconductor memory device and a method of manufacturing the same. In particular, this invention relates to a structure of a semiconductor memory device having a trench capacitor in a memory cell, and a method of manufacturing the same.
2. Description of the Related Art
The integration density of semiconductor integrated circuits has become higher and higher in recent years. In particular, DRAMs (Dynamic Random Access Memory) have made remarkable progress in this respect. To achieve higher integration density in a DRAM cell having 1 transistor and 1 capacitor, it is required to microminiaturize the parts. With micro-miniaturization of a DRAM cell, a source diffusion layer (or drain diffusion layer) of a transistor of the cell is also reduced.
A DRAM using a trench capacitor as a capacitor forming a DRAM cell is known. Further, as a strap contact for connecting a source region of a memory cell transistor and an electrode of a trench capacitor, which form a DRAM cell, used is a BS (Buried Strap) contact layer. The BS contact layer is formed to be buried in a semiconductor substrate on which the DRAM cell is formed.
However, with microminiaturization of DRAM cells, the volume of a BS contact layer is reduced. This causes increase in the resistance value of the BS contact layer. As a method of solving this problem, it is one choice to adopt an SS (Surface Strap) contact layer forming a strap contact layer on a surface of the semiconductor substrate. An example of the structure of a DRAM having an SS contact layer is explained below. FIG. 31 is a cross-sectional view of a main part of a conventional DRAM.
In a semiconductor substrate 1, a trench 2 is formed. A plate electrode 3 formed of an N type diffusion layer for a capacitor electrode is provided around a lower portion of the trench 2, in the semiconductor substrate 1. An NO film 4 (formed of a silicon nitride film and a silicon oxide film) being a dielectric film of a capacitor is provided on an inner surface of the lower portion of the trench 2. A polysilicon layer 5 serving as an electrode of the capacitor is provided on the NO film 4 in the trench 2. On the inner surface of the trench 2 above the polysilicon layer 5, a color oxide film 6 is provided to electrically insulate the plate electrode 3 from a source or a drain diffusion layer of a memory cell transistor formed on the semiconductor substrate 1. In the trench 2, a polysilicon layer 7 being a wiring layer for contact with the polysilicon layer 5 is provided on the color oxide film 6. A element-isolating region 8 is provided in the surface of the semiconductor substrate 1, to electrically separate the device from the adjacent device.
On the semiconductor substrate 1, provided is a memory cell transistor having a gate insulating film 9, a polysilicon gate electrode layer 10, a WSi gate electrode layer 11, a gate cap insulating film 12, a gate side wall insulating film 13, a source diffusion layer 14 and a drain diffusion layer 15. Further, on the element-isolating region 8, provided is a pass word-line having a polysilicon gate electrode layer 16, a WSi gate electrode layer 17, a gate cap insulating film 18 and a gate side wall insulating film 19. An SS contact layer 40 serving as a contact layer between the polysilicon layer 7 and the source diffusion layer 14 is provided on the polysilicon layer 7 and the source diffusion layer 14.
If the SS contact layer 40 shown in FIG. 31 is formed, an oxide film (Trench Top Oxide, hereinafter referred to as “TTO”) formed on the trench capacitor (specifically, polysilicon layer 7) is etched back and thereby the polysilicon layer 7 serving as a wiring layer is exposed. Then, polysilicon serving as the SS contact layer 40 is deposited on the polysilicon layer 7. In such a case, in etchback of the TTO, the color oxide film 6 and the element-isolating region 8 are undesirably etched back, too.
Depositing polysilicon for the SS contact layer 40 in this state produces a structure where the SS contact layer 40 contacts also on the side surface of the active region on which the memory cell transistor is formed. This causes diffusion of impurities from the SS contact layer 40 to the active region, and undesirably increases junction depth of the source diffusion layer 14 of the memory cell transistor. This causes deterioration of the property of the memory cell transistor.
Further, if the color oxide film 6 and the element-isolating region 8 are deeply etched, the junction depth is further increased, and the property of the memory cell transistor is further deteriorated. Such a problem becomes more obvious with size reduction in the design rule.
As related art of this kind, disclosed is a technique of reducing the resistance of a buried strap (refer to Jpn. Pat. Appln. KOKAI Pub. No. 2003-282734).